The present invention relates to output driver circuits generally and, more particularly, to a high voltage tolerant output driver circuit for mixed power supply levels.
The trend in modern central processing units (CPUs) and microprocessors is to reduce the power supply operating voltage in order to reduce power consumption and increase the chip density. The power supply reduction may impact other performance considerations as well. Due to the design considerations, memory devices, such as dynamic random access memories (DPAMs), may operate at a different supply voltage than the CPU. Some devices also may be required to use more than one power supply voltage so they can signal a CPU related device at one voltage and other devices at another voltage. The signals are generally generated by one circuit and are received by another circuit.
One such configuration occurs with modern microprocessors that operate with a nominal power supply voltage of about 2.5 V (or lower) while other circuits in the computer operate with a power supply voltage of about 3.3 V. To facilitate communication between devices operating at different voltages, an output driver circuit is used.
Referring to FIG. 1, a circuit 10 is illustrating a conventional approach. The circuit 10 generally comprises a core logic circuit 12, an output driver circuit 14 and a circuit 16. The circuit 16 is an external device. The circuit 12 and the circuit 16 form a circuit 15. The output driver circuit 14 receives a pullup signal PU and a pulldown signal PD from the core logic 12. The pull signals PU and PD swing between ground and a core supply voltage level VCC_CORE. The output driver circuit 14 comprises a level shifter 17, a level shifter 18, a pad driver circuit 20, and a tolerance circuit 24. The level shifters 17 and 18 shift the levels of the pull signals PU and PD, respectively, from the voltage VCC_CORE to a second supply voltage VCCIO. The level shifters 17 and 18 generate a level shifted pullup signal PUG and a level shifted pulldown signal PDG, respectively. The level shifted pull signals PUG and PDG are presented to the pad driver circuit 20. The pad driver circuit 20 generates a signal PAD at an output 22 in response to the level shifted pull signals PUG and PDG. The signal PAD is presented to a pad 30. The tolerance circuit 24 provides high voltage tolerance should the signal PAD be connected to a device (i.e., the circuit 16) operating at a higher voltage than the second supply voltage (i.e., where VCCEXT greater than VCCIO). The tolerance circuit 24 generates a first output signal NSUB at a first output 26 and a second output signal HV at a second output 28 in response to the second supply voltage VCCIO and the voltage of the signal PAD. The output signals NSUB and HV are used to disable a PMOS pull-up device in the pad driver circuit when the pad voltage is higher than the second supply voltage.
FIG. 2 is a diagram of a circuit 14xe2x80x2 illustrating a conventional approach for implementing a high voltage tolerance circuit 20xe2x80x2. The circuit 20xe2x80x2 generally comprises a transistor 46, a transistor 48, a transistor 50, transistor 51 and a pump circuit 56. The transistor 46 is an NMOS device connected between the core circuitry 12 (thin oxide devices) and a gate of the output driver PMOS pull-up transistor 50. The pump circuit 56 is used to pump the gate of the NMOS pass transistor 46 to a voltage above VCCIO (e.g., VCCIO+Vtn). The voltage Vtn may be a transistor threshold voltage. By having the gate at a voltage above VCCIO, the core VCC level is passed to the gate of the PMOS pull-up device 50 to ensure the device 50 can be shut off during normal operation. The PMOS transistor 48 allows the tolerance circuit 24 to pull the gate of the PMOS pull-up device 50 to the pad level VCCEXT for high voltage tolerance. The purpose of the tolerance circuit 24 is to detect when the pad voltage is higher than the voltage VCCIO and force the nwell of transistor 50 and the gate of transistor 50 to the pad voltage. This avoids forward biasing the diode formed by the drain and nwell (e.g., body) of the transistor 50 that would otherwise become a latch-up risk.
FIG. 3 illustrates another conventional approach of an output driver circuit 14xe2x80x3. A PMOS transistor 78 is placed in series with the output driver PMOS pull-up device 76. A gate of the PMOS transistor 78 is controlled by a signal HV generated by the tolerance circuit 24. During normal operation, the signal HV is always low (xe2x80x9c0xe2x80x9d). When the pad voltage is higher than the supply voltage (i.e., VCCEXT greater than VCCIO), the tolerance circuit 24 detects the difference and pulls the gate of the PMOS transistor 78 to the pad voltage level, shutting off the PMOS transistor 78.
The conventional approaches illustrated for implementing high voltage tolerance output drivers have added circuitry to the pad driver to shut off the PMOS pull-up device. The additional circuitry shown in FIG. 2 requires a charge pump and an NMOS pass gate transistor 46. The additional circuitry shown in FIG. 3 (i.e., the PMOS transistor 78) may limit the drive capability.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal, (ii) a second input signal and (iii) a voltage control signal. The second circuit configured to generate (i) an output signal in response to the first and the second control signals and (ii) the voltage control signal in response to a pad voltage.
The objects, features and advantages of the present invention include providing an output driver circuit that may (i) provide a level shifting circuit, powered by the output of a tolerance circuit that may be the maximum of either a supply voltage (VCCIO) or a voltage presented at the pad, (ii) provide a level shifting circuit that isolates the internal core from the I/O interface to protect the core devices from high voltage levels presented on the pad, (iii) disable the output driver PMOS pull-up device for pad voltages higher than the supply voltage, and/or (iv) combine level shifter and disabling features for a high voltage tolerance circuit.